This invention relates to a technology for regulating internal impedance of output buffers of a semiconductor device. For example, the invention relates to a technology that will be effective when applied to impedance matching of data output buffers in a semiconductor device such as an SRAM (Static Random Access Memory).
To reduce influences of signal reflection through a transmission line, it is necessary to highly accurately establish impedance matching that brings an internal impedance viewed from an external terminal of a semiconductor device into conformity with the impedance of a transmission line.
Because the internal impedance changes in accordance with driving capacity of output buffers, JP-A-05-166931, (especially in FIGS. 1–3) describes a circuit construction in which a plurality of clamp resistors are connected in parallel on the side of a ground potential of a push-pull output circuit and are taken out to pad electrodes of a semiconductor chip and one of the pad electrodes is selected and connected to the ground potential of the circuit at the time of assembly so that the internal impedance can be selected in accordance with the driving capacity of the output buffers.